library ieee;
use ieee.std_logic_1164.all;

entity VHDLNot is
    port(
         LINE : in std_logic;          
         INVERTED_LINE : out std_logic 
    );     
end VHDLNot;


architecture Dataflow of VHDLNot is 

begin 
  
   INVERTED_LINE <= not LINE;

end Dataflow;