Features

  • CPU: Microchip SAMA5D27 MPU (Cortex A5 single core @500MHz)
    • On-the-fly AES encryption/decryption on DDR and QSPI memories
    • 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
    • 128-Kbyte L2 cache configurable to be used as an internal 32 bit single cycle SRAM
    • 5 Kbytes of internal scrambled SRAM:
      • 1 Kbyte non-erasable on tamper detection
      • 4 Kbytes erasable on tamper detection
    • 256 bits of scrambled and erasable registers
    • Up to seven tamper pins for static or dynamic intrusion detections
    • Secure Boot Loader
    • RTC including time-stamping on security intrusions
    • Programmable fuse box with 544 fuse bits including JTAG protection and BMS
    • NAND controller
    • ARM NEON (tm) SIMD Media Processing Engine
    • Hardware Floating Point Unit
    • Hardware cryptography
      • SHA: SHA1, SHA224, SHA256, SHA384, SHA512; compliant with FIPS PUB180-2
      • AES: 256, 192, 128 bit key algorithm; compliant with FIPS PUB 197
      • TDES: two-key or three-key algorithms; compliant with FIPS PUB 46-3
      • True Random Number Generator (TRNG); compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs 140-2 and 140-3
  • RAM: 256 MByte of DDR3L RAM @ 166MHz
  • FLASH: Up to 128 MByte of QSPI flash memory @ 133MHz
  • Extended temperature range: -40°C; to +85°C
  • Small form factor: 40 x 30 (3.5mm height over carrier board)
  • Weight: 5g
  • 10 layers VIPPO technology PCB
  • Single power supply at 3.3 Volt DC
  • Ultra Low-power mode with fast wakeup capability
  • Low-power Backup mode with 5-Kbyte SRAM and SleepWalking (tm) features
  • Wakeup from up to eight wakeup pins, UART reception, analog comparison
  • Extended Backup mode with DDR in Self-Refresh mode
  • Low power consumption:
    • 100% CPU (memtester): 143mA @ 3.3V (472mW)
    • idle (at Linux prompt): 84mA @ 3.3V (277mW)
    • Ultra LowPower 1 (ULP1) (resume in 159ms): 5.3mA @ 3.3V (17mW)
  • Low EMI (multiple ground planes and impedance controlled tracks)
  • RoHS compliant
  • Long term availability

Signals

Two Hirose 6Gbps 100-pin connectors 0.4 mm pitch, with all the CPU signals:

  • 10/100 Mbit ethernet GMAC with IEEE1588 Precision Time Protocol (PTP)
  • RGB i/f @ 24 bit for LCD TFT
  • Resistive and capacitive touch panel interface
  • Synchronous Serial Controllers SSC/I2S (up to 2)
  • TWI compatible I2C i/f (up to 7) up to 400 Kbits/s supporting I2C and SMBUS
  • SPI bus i/f (up to 7)
  • Quad Serial Peripheral Interfaces QSPI (up to 2)
  • One Stereo ClassD amplifier
  • Peripheral Touch Controller PTC with up t o 8X-lines and 8Y-lines (64-channel capacitive touch)
  • Pulse Density Modulation Interface Controller PDMIC (digital microphone)
  • Two master CAN-FD MCAN controllers with SRAM-based mailboxes
  • GPIO lines (up to 128)
  • A/D @ 12 bit (up to 12)
  • Serial ports (up to 10: five USART and five UART)
  • One additional Rx only UART in backup area RXLP
  • One analog comparator ACC in backup area
  • 2 high-speed USB Host, or 1 USB Host and 1 USB device
  • 1 high-speed Inter-Chip HSIC USB port interface
  • Two high-speed memory card hosts (SDIO, SD or MMC):
    • SDMMC0: SD 3.0, eMMC 4.51, 8 bits
    • SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
  • ITU-RBT.601/656/1120 Image Sensor Controller ISC supporting up to 5M-pixel sensors
  • Two 3-channel 32-bit Timer/Counters TC , supporting PWM modes (up to 6 out)
  • One full-featured 4-channel 16-bit PWM controller
  • Programmable clock (up to 3)
  • JTAG port
  • Debug serial port
  • Battery input for internal RTC, backup area and backup RAM