Acqua A5 pinout

  • Pin # Acqua A5 pin name
  • IC Pin Atmel pin name
  • Default Line functions assigned by default by our Linux distribution
  • Alt Alternative line functions that can be set changing the device tree binding
  • KID Kernel ID using sysfs gpio interface
  • Note Any notes about the pin
  • Reset state Line state at CPU reset
    • PIO indicates whether the PIO Line resets in I/O mode
    • A indicates whether the peripheral A mode
    • I/O Indicates whether the signal is input or output state.
    • PU/PD Indicates whether Pull-Up, Pull-Down or nothing is enabled.
    • ST Indicates if Schmitt Trigger is enabled.

The PIO lines called PAx, PBx, PCx, PDx and PEx can be configured in up to four different ways. Please refer to the SAMA5D3 datasheet at page 11 to have a complete reference.

Be carefull to check whether the line reset state is compatible with your application board because it is changed to the Linux default config during the bootstrap after at least 500 ms.

Pin # IC Pin Default Alt Alt KID Note Reset state
J1.1 ETH_TXP
J1.2 ETH_RXN
J1.3 ETH_TXN
J1.4 ETH_RXP
J1.5 ETH_GND
J1.6 ETH_3V3
J1.7 ETH_LED1 Link
J1.8 ETH_LED2 Traffic
J1.9 PA1 LCD DAT1 GPIO 1 PIO,I,PU,ST
J1.10 PA0 LCD DAT0 GPIO 0 PIO,I,PU,ST
J1.11 PA3 LCD DAT3 GPIO 3 PIO,I,PU,ST
J1.12 PA2 LCD DAT2 GPIO 2 PIO,I,PU,ST
J1.13 PA5 LCD DAT5 GPIO 5 PIO,I,PU,ST
J1.14 PA4 LCD DAT4 GPIO 4 PIO,I,PU,ST
J1.15 PA7 LCD DAT7 GPIO 7 PIO,I,PU,ST
J1.16 PA6 LCD DAT6 GPIO 6 PIO,I,PU,ST
J1.17 PA9 LCD DAT9 GPIO 9 PIO,I,PU,ST
J1.18 PA8 LCD DAT8 GPIO 8 PIO,I,PU,ST
J1.19 PA11 LCD DAT11 GPIO 11 PIO,I,PU,ST
J1.20 PA10 LCD DAT10 GPIO 10 PIO,I,PU,ST
J1.21 PA13 LCD DAT13 GPIO 13 PIO,I,PU,ST
J1.22 PA12 LCD DAT12 GPIO 12 PIO,I,PU,ST
J1.23 PA15 LCD DAT15 GPIO 15 PIO,I,PU,ST
J1.24 PA14 LCD DAT14 GPIO 14 PIO,I,PU,ST
J1.25 PC13 LCD DAT17 MCI2_DA2 TIOB1 77 PIO,I,PU,ST
J1.26 PC14 LCD DAT16 MCI2_DA3 TCLK1 78 PIO,I,PU,ST
J1.27 PC11 LCD DAT19 MCI2_DA0 75 PIO,I,PU,ST
J1.28 PC12 LCD DAT18 MCI2_DA1 TIOA1 76 PIO,I,PU,ST
J1.29 PC15 LCD DAT21 MCI2_CK PCK2 79 PIO,I,PU,ST
J1.30 PC10 LCD DAT20 MCI2_CDA 74 PIO,I,PU,ST
J1.31 PE28 LCD DAT23 GPIO TIOB2 156 PIO,I,PU,ST
J1.32 PE27 LCD DAT22 GPIO TIOA2 155 PIO,I,PU,ST
J1.33 PA25 LCD DISP GPIO 25 PIO,I,PU,ST
J1.34 GND
J1.35 PA27 LCD HSYNC GPIO 27 PIO,I,PU,ST
J1.36 PA28 LCD PCK GPIO 28 PIO,I,PU,ST
J1.37 PA29 LCD DEN GPIO 29 PIO,I,PU,ST
J1.38 PA26 LCD VSYNC GPIO 26 PIO,I,PU,ST
J1.39 PA24 LCD PWM GPIO 24 PIO,I,PU,ST
J1.40 PD20 AD0 GPIO 116 PIO,I,PU,ST
J1.41 PD21 AD1 GPIO 117 PIO,I,PU,ST
J1.42 PD22 AD2 GPIO 118 PIO,I,PU,ST
J1.43 PD23 AD3 GPIO 119 PIO,I,PU,ST
J1.44 PD24 AD4 GPIO 120 PIO,I,PU,ST
J1.45 PD25 AD5 GPIO 121 PIO,I,PU,ST
J1.46 PD26 AD6 GPIO 122 PIO,I,PU,ST
J1.47 PD27 AD7 GPIO 123 PIO,I,PU,ST
J1.48 PD28 AD8 GPIO 124 PIO,I,PU,ST
J1.49 PD29 AD9 GPIO 125 PIO,I,PU,ST
J1.50 ADVREF


Pin # IC Pin Default Alt Alt KID Note Reset state
J2.1 PD31 AD11 GPIO 127 PIO,I,PU,ST
J2.2 PD30 AD10 GPIO 126 PIO,I,PU,ST
J2.3 PD19 A/D TRIGGER GPIO 115 PIO,I,PU,ST
J2.4 GND
J2.5 PD13 SPI0_NCS0 GPIO 109 PIO,I,PU,ST
J2.6 PD12 SPI0_CK GPIO 108 PIO,I,PU,ST
J2.7 PD11 SPI0_MOSI GPIO 107 PIO,I,PU,ST
J2.8 PD10 SPI0_MISO GPIO 106 PIO,I,PU,ST
J2.9 PD15 CTS0 (/dev/ttyS1) SPI0_NCS2 111 PIO,I,PU,ST
J2.10 PD14 SPI0_NCS1 GPIO 110 PIO,I,PU,ST
J2.11 PD17 RXD0 (/dev/ttyS1) GPIO 113 PIO,I,PU,ST
J2.12 PD16 RTS0 (/dev/ttyS1) SPI0_NCS3 112 PIO,I,PU,ST
J2.13 PB2 GPIO SSC_TK1 34 PIO,I,PU,ST
J2.14 PD18 TXD0 (/dev/ttyS1) GPIO 114 PIO,I,PU,ST
J2.15 PB6 GPIO SSC_TD1 38 PIO,I,PU,ST
J2.16 PB3 GPIO SSC_TF1 35 PIO,I,PU,ST
J2.17 PB7 GPIO SSC_RK1 39 PIO,I,PU,ST
J2.18 PB11 GPIO SSC_RD1 43 PIO,I,PU,ST
J2.19 PB10 GPIO SSC_RF1 42 PIO,I,PU,ST
J2.20 USBA_P USB A
J2.21 3V3
J2.22 USBA_N USB A
J2.23 PB4 GPIO PWMH1 36 PIO,I,PU,ST
J2.24 USBB_P USB B
J2.25 PB5 GPIO PWML1 37 PIO,I,PU,ST
J2.26 USBB_N USB B
J2.27 GND
J2.28 USBC_P USB C
J2.29 PB0 GPIO PWMH0 32 PIO,I,PU,ST
J2.30 USBC_N USB C
J2.31 PB1 GPIO PWML0 33 PIO,I,PU,ST
J2.32 PB14 GPIO 46 PIO,I,PU,ST
J2.33 PB8 GPIO PWMH2 40 PIO,I,PU,ST
J2.34 PB15 GPIO 47 PIO,I,PU,ST
J2.35 PB9 GPIO PWML2 41 PIO,I,PU,ST
J2.36 PB16 GPIO 48 PIO,I,PU,ST
J2.37 PB12 GPIO PWMH3 44 PIO,I,PU,ST
J2.38 PB17 GPIO 49 PIO,I,PU,ST
J2.39 PB13 GPIO PWML3 45 PIO,I,PU,ST
J2.40 PB18 GPIO 50 PIO,I,PU,ST
J2.41 GND PIO,I,PU,ST
J2.42 PB27 RTS1 (/dev/ttyS2) GPIO 59 PIO,I,PU,ST
J2.43 PB26 CTS1 (/dev/ttyS2) GPIO 58 PIO,I,PU,ST
J2.44 PB25 GPIO 57 PIO,I,PU,ST
J2.45 PB28 RXD1 (/dev/ttyS2) GPIO 60 PIO,I,PU,ST
J2.46 PB29 TXD1 (/dev/ttyS2) GPIO 61 PIO,I,PU,ST
J2.47 WKUP Read below
J2.48 SHDN Read below
J2.49 POWER_EN Read below
J2.50 NRST Read below


  • WKUP is a means to wake up the CPU from the shutdown state before the programmed time on a programmable (rise, fall or both ) external event. If not used can be left disconnected.
  • SHDN: it is the SHDN pin of the A5 CPU. If instructed to do so, the CPU will lower this signal to disable an external 3.3V power regulator powering the Acqua board. It will work only if you supply a battery backup voltage between 2V and 3V on the VBAT pin. In this way you can shutdown completely the power for the Acqua board (power consumption 0) and wake it up after some time. If not used can be left disconnected.
  • POWER_EN: disables some of the internal regulators for factory internal tests. Left it unconnected.
  • NRST is a bidirectional external RESET for the CPU. It means you can reset the A5 CPU from outside but also use the power supervisor inside the Acqua board to reset external chips. The power supervisor onboard will wait for the power to be stabilized for 140ms before raising the NRST line.
    If not used can be left disconnected.

Pin # IC Pin Default Alt Alt KID Note Reset state
J3.1 BOOT_OFF Read below PIO,I,PU,ST
J3.2 VBAT Read below PIO,I,PU,ST
J3.3 PB30 DRXD Debug port PIO,I,PU,ST
J3.4 PB31 DTXD Debug port PIO,I,PU,ST
J3.5 PE17 RTS3 (/dev/ttyS4) GPIO 145 A,I,PD,ST
J3.6 PE16 CTS3 (/dev/ttyS4) GPIO 144 A,I,PD,ST
J3.7 PE19 TXD3 (/dev/ttyS4) GPIO 147 A,I,PD,ST
J3.8 PE18 RXD3 (/dev/ttyS4) GPIO 146 A,I,PD,ST
J3.9 PE15 GPIO 143 A,I,PD,ST
J3.10 PE23 CTS2 (/dev/ttyS3) GPIO 151 A,I,PD,ST
J3.11 PE24 RTS2 (/dev/ttyS3) GPIO 152 A,I,PD,ST
J3.12 PE25 RXD2 (/dev/ttyS3) GPIO 153 A,I,PD,ST
J3.13 PE26 TXD2 (/dev/ttyS3) GPIO 155 A,I,PD,ST
J3.14 PE20 GPIO 148 A,I,PD,ST
J3.15 PB22 GPIO MCI1_DA2 54 PIO,I,PU,ST
J3.16 PB23 GPIO MCI1_DA3 55 PIO,I,PU,ST
J3.17 PB19 GPIO MCI1_CDA 51 PIO,I,PU,ST
J3.18 PB21 GPIO MCI1_DA1 53 PIO,I,PU,ST
J3.19 PB24 GPIO MCI1_CK 56 PIO,I,PU,ST
J3.20 PB20 GPIO MCI1_DA0 52 PIO,I,PU,ST
J3.21 3V3 PIO,I,PU,ST
J3.22 PC23 GPIO SPI1_MOSI 87 PIO,I,PU,ST
J3.23 PC25 GPIO SPI1_NCS0 89 PIO,I,PU,ST
J3.24 PC22 GPIO SPI1_MISO 86 PIO,I,PU,ST
J3.25 PC24 GPIO SPI1_SPCK 88 PIO,I,PU,ST
J3.26 PC26 GPIO SPI1_NCS1 TWD1 90 PIO,I,PU,ST
J3.27 GND PIO,I,PU,ST
J3.28 PC27 GPIO SPI1_NCS2 TWCK1 91 PIO,I,PU,ST
J3.29 PC28 GPIO SPI1_NCS3 92 PIO,I,PU,ST
J3.30 PC30 GPIO UTXD0 (/dev/ttyS5) 94 PIO,I,PU,ST
J3.31 PC29 GPIO URXD0 (/dev/ttyS5) 93 PIO,I,PU,ST
J3.32 PC31 GPIO 95 PIO,I,PU,ST
J3.33 PA17 GPIO 17 PIO,I,PU,ST
J3.34 PA16 GPIO 16 PIO,I,PU,ST
J3.35 PA19 GPIO TXCK2 19 PIO,I,PU,ST
J3.36 PA18 GPIO TWD2 18 PIO,I,PU,ST
J3.37 PA21 GPIO 21 PIO,I,PU,ST
J3.38 PA20 GPIO 20 PIO,I,PU,ST
J3.39 PA23 GPIO 23 PIO,I,PU,ST
J3.40 PA22 GPIO 22 PIO,I,PU,ST
J3.41 PA31 TWCK0 GPIO UTXD1 (/dev/ttyS6) 31 PIO,I,PU,ST
J3.42 PA30 TWD0 GPIO URXD1 (/dev/ttyS6) 30 PIO,I,PU,ST
J3.43 PE31 GPIO 159 PIO,I,PD,ST
J3.44 PE29 GPIO 157 PIO,I,PD,ST
J3.45 PC16 SSC_TK0 GPIO 80 PIO,I,PU,ST
J3.46 PC17 SSC_TF0 GPIO 81 PIO,I,PU,ST
J3.47 PC18 SSC_TD0 GPIO 82 PIO,I,PU,ST
J3.48 PC19 SSC_RK0 GPIO 83 PIO,I,PU,ST
J3.49 PC20 SSC_RF0 GPIO 84 PIO,I,PU,ST
J3.50 PC21 SSC_RD0 GPIO 85 PIO,I,PU,ST


  • BOOT_OFF: keeping this line low at startup will disable the boot of the NAND FLASH chip, in order to be able to re-program it with the Atmel tool SAM-BA. If not used can be left disconnected.
  • VBAT: if you need the internal RTC working you have to connect a backup battery here, also to enable the timed wakeup as explained above. If not used can be left disconnected.