Board pinouts

Here are the pinout map of all the boards we made

Acqua A5 pinout

Pin # Acqua A5 pin name
IC Pin Microchip pin name
Default Line functions assigned by default by our Linux distribution
Alt Alternative line functions that can be set changing the device tree binding
KID Kernel ID using sysfs gpio interface
Note Any notes about the pin
Reset state Line state at CPU reset
- PIO indicates whether the PIO Line resets in I/O mode
- A indicates whether the peripheral A mode
- I/O Indicates whether the signal is input or output state.
- PU/PD Indicates whether Pull-Up, Pull-Down or nothing is enabled.
- ST Indicates if Schmitt Trigger is enabled.

The PIO lines called PAx, PBx, PCx, PDx and PEx can be configured in up to four different ways. Please refer to the SAMA5D3 datasheet at page 11 to have a complete reference.

Be carefull to check whether the line reset state is compatible with your application board because it is changed to the Linux default config during the bootstrap after at least 500 ms.

Pin #	IC Pin	Default	Alt	Alt	KID	Note	Reset state
J1.1	ETH_TXP
J1.2	ETH_RXN
J1.3	ETH_TXN
J1.4	ETH_RXP
J1.5	ETH_GND
J1.6	ETH_3V3
J1.7	ETH_LED1					Link
J1.8	ETH_LED2					Traffic
J1.9	PA1	LCD DAT1	GPIO		1		PIO,I,PU,ST
J1.10	PA0	LCD DAT0	GPIO		0		PIO,I,PU,ST
J1.11	PA3	LCD DAT3	GPIO		3		PIO,I,PU,ST
J1.12	PA2	LCD DAT2	GPIO		2		PIO,I,PU,ST
J1.13	PA5	LCD DAT5	GPIO		5		PIO,I,PU,ST
J1.14	PA4	LCD DAT4	GPIO		4		PIO,I,PU,ST
J1.15	PA7	LCD DAT7	GPIO		7		PIO,I,PU,ST
J1.16	PA6	LCD DAT6	GPIO		6		PIO,I,PU,ST
J1.17	PA9	LCD DAT9	GPIO		9		PIO,I,PU,ST
J1.18	PA8	LCD DAT8	GPIO		8		PIO,I,PU,ST
J1.19	PA11	LCD DAT11	GPIO		11		PIO,I,PU,ST
J1.20	PA10	LCD DAT10	GPIO		10		PIO,I,PU,ST
J1.21	PA13	LCD DAT13	GPIO		13		PIO,I,PU,ST
J1.22	PA12	LCD DAT12	GPIO		12		PIO,I,PU,ST
J1.23	PA15	LCD DAT15	GPIO		15		PIO,I,PU,ST
J1.24	PA14	LCD DAT14	GPIO		14		PIO,I,PU,ST
J1.25	PC13	LCD DAT17	MCI2_DA2	TIOB1	77		PIO,I,PU,ST
J1.26	PC14	LCD DAT16	MCI2_DA3	TCLK1	78		PIO,I,PU,ST
J1.27	PC11	LCD DAT19	MCI2_DA0		75		PIO,I,PU,ST
J1.28	PC12	LCD DAT18	MCI2_DA1	TIOA1	76		PIO,I,PU,ST
J1.29	PC15	LCD DAT21	MCI2_CK	PCK2	79		PIO,I,PU,ST
J1.30	PC10	LCD DAT20	MCI2_CDA		74		PIO,I,PU,ST
J1.31	PE28	LCD DAT23	GPIO	TIOB2	156		PIO,I,PU,ST
J1.32	PE27	LCD DAT22	GPIO	TIOA2	155		PIO,I,PU,ST
J1.33	PA25	LCD DISP	GPIO		25		PIO,I,PU,ST
J1.34	GND
J1.35	PA27	LCD HSYNC	GPIO		27		PIO,I,PU,ST
J1.36	PA28	LCD PCK	GPIO		28		PIO,I,PU,ST
J1.37	PA29	LCD DEN	GPIO		29		PIO,I,PU,ST
J1.38	PA26	LCD VSYNC	GPIO		26		PIO,I,PU,ST
J1.39	PA24	LCD PWM	GPIO		24		PIO,I,PU,ST
J1.40	PD20	AD0	GPIO		116		PIO,I,PU,ST
J1.41	PD21	AD1	GPIO		117		PIO,I,PU,ST
J1.42	PD22	AD2	GPIO		118		PIO,I,PU,ST
J1.43	PD23	AD3	GPIO		119		PIO,I,PU,ST
J1.44	PD24	AD4	GPIO		120		PIO,I,PU,ST
J1.45	PD25	AD5	GPIO		121		PIO,I,PU,ST
J1.46	PD26	AD6	GPIO		122		PIO,I,PU,ST
J1.47	PD27	AD7	GPIO		123		PIO,I,PU,ST
J1.48	PD28	AD8	GPIO		124		PIO,I,PU,ST
J1.49	PD29	AD9	GPIO		125		PIO,I,PU,ST
J1.50		ADVREF

Pin #	IC Pin	Default	Alt	KID	Note	Reset state
J2.1	PD31	AD11	GPIO	127		PIO,I,PU,ST
J2.2	PD30	AD10	GPIO	126		PIO,I,PU,ST
J2.3	PD19	A/D TRIGGER	GPIO	115		PIO,I,PU,ST
J2.4	GND
J2.5	PD13	SPI0_NCS0	GPIO	109		PIO,I,PU,ST
J2.6	PD12	SPI0_CK	GPIO	108		PIO,I,PU,ST
J2.7	PD11	SPI0_MOSI	GPIO	107		PIO,I,PU,ST
J2.8	PD10	SPI0_MISO	GPIO	106		PIO,I,PU,ST
J2.9	PD15	CTS0 (/dev/ttyS1)	SPI0_NCS2	111		PIO,I,PU,ST
J2.10	PD14	SPI0_NCS1	GPIO	110		PIO,I,PU,ST
J2.11	PD17	RXD0 (/dev/ttyS1)	GPIO	113		PIO,I,PU,ST
J2.12	PD16	RTS0 (/dev/ttyS1)	SPI0_NCS3	112		PIO,I,PU,ST
J2.13	PB2	GPIO	SSC_TK1	34		PIO,I,PU,ST
J2.14	PD18	TXD0 (/dev/ttyS1)	GPIO	114		PIO,I,PU,ST
J2.15	PB6	GPIO	SSC_TD1	38		PIO,I,PU,ST
J2.16	PB3	GPIO	SSC_TF1	35		PIO,I,PU,ST
J2.17	PB7	GPIO	SSC_RK1	39		PIO,I,PU,ST
J2.18	PB11	GPIO	SSC_RD1	43		PIO,I,PU,ST
J2.19	PB10	GPIO	SSC_RF1	42		PIO,I,PU,ST
J2.20	USBA_P					USB A
J2.21	3V3
J2.22	USBA_N					USB A
J2.23	PB4	GPIO	PWMH1	36		PIO,I,PU,ST
J2.24	USBB_P					USB B
J2.25	PB5	GPIO	PWML1	37		PIO,I,PU,ST
J2.26	USBB_N					USB B
J2.27	GND
J2.28	USBC_P					USB C
J2.29	PB0	GPIO	PWMH0	32		PIO,I,PU,ST
J2.30	USBC_N					USB C
J2.31	PB1	GPIO	PWML0	33		PIO,I,PU,ST
J2.32	PB14	GPIO		46		PIO,I,PU,ST
J2.33	PB8	GPIO	PWMH2	40		PIO,I,PU,ST
J2.34	PB15	GPIO		47		PIO,I,PU,ST
J2.35	PB9	GPIO	PWML2	41		PIO,I,PU,ST
J2.36	PB16	GPIO		48		PIO,I,PU,ST
J2.37	PB12	GPIO	PWMH3	44		PIO,I,PU,ST
J2.38	PB17	GPIO		49		PIO,I,PU,ST
J2.39	PB13	GPIO	PWML3	45		PIO,I,PU,ST
J2.40	PB18	GPIO		50		PIO,I,PU,ST
J2.41	GND					PIO,I,PU,ST
J2.42	PB27	RTS1 (/dev/ttyS2)	GPIO	59		PIO,I,PU,ST
J2.43	PB26	CTS1 (/dev/ttyS2)	GPIO	58		PIO,I,PU,ST
J2.44	PB25	GPIO		57		PIO,I,PU,ST
J2.45	PB28	RXD1 (/dev/ttyS2)	GPIO	60		PIO,I,PU,ST
J2.46	PB29	TXD1 (/dev/ttyS2)	GPIO	61		PIO,I,PU,ST
J2.47	WKUP				Read below
J2.48	SHDN				Read below
J2.49	POWER_EN				Read below
J2.50	NRST				Read below

WKUP is a means to wake up the CPU from the shutdown state before the programmed time on a programmable (rise, fall or both ) external event. If not used can be left disconnected.
SHDN: it is the SHDN pin of the A5 CPU. If instructed to do so, the CPU will lower this signal to disable an external 3.3V power regulator powering the Acqua board. It will work only if you supply a battery backup voltage between 2V and 3V on the VBAT pin. In this way you can shutdown completely the power for the Acqua board (power consumption 0) and wake it up after some time. If not used can be left disconnected.
POWER_EN: disables some of the internal regulators for factory internal tests. Left it unconnected.
NRST is a bidirectional external RESET for the CPU. It means you can reset the A5 CPU from outside but also use the power supervisor inside the Acqua board to reset external chips. The power supervisor onboard will wait for the power to be stabilized for 140ms before raising the NRST line.
If not used can be left disconnected.

Pin #	IC Pin	Default	Alt	Alt	KID	Note	Reset state
J3.1	BOOT_OFF					Read below	PIO,I,PU,ST
J3.2	VBAT					Read below	PIO,I,PU,ST
J3.3	PB30	DRXD				Debug port	PIO,I,PU,ST
J3.4	PB31	DTXD				Debug port	PIO,I,PU,ST
J3.5	PE17	RTS3 (/dev/ttyS4)	GPIO		145		A,I,PD,ST
J3.6	PE16	CTS3 (/dev/ttyS4)	GPIO		144		A,I,PD,ST
J3.7	PE19	TXD3 (/dev/ttyS4)	GPIO		147		A,I,PD,ST
J3.8	PE18	RXD3 (/dev/ttyS4)	GPIO		146		A,I,PD,ST
J3.9	PE15	GPIO			143		A,I,PD,ST
J3.10	PE23	CTS2 (/dev/ttyS3)	GPIO		151		A,I,PD,ST
J3.11	PE24	RTS2 (/dev/ttyS3)	GPIO		152		A,I,PD,ST
J3.12	PE25	RXD2 (/dev/ttyS3)	GPIO		153		A,I,PD,ST
J3.13	PE26	TXD2 (/dev/ttyS3)	GPIO		155		A,I,PD,ST
J3.14	PE20	GPIO			148		A,I,PD,ST
J3.15	PB22	GPIO	MCI1_DA2		54		PIO,I,PU,ST
J3.16	PB23	GPIO	MCI1_DA3		55		PIO,I,PU,ST
J3.17	PB19	GPIO	MCI1_CDA		51		PIO,I,PU,ST
J3.18	PB21	GPIO	MCI1_DA1		53		PIO,I,PU,ST
J3.19	PB24	GPIO	MCI1_CK		56		PIO,I,PU,ST
J3.20	PB20	GPIO	MCI1_DA0		52		PIO,I,PU,ST
J3.21	3V3						PIO,I,PU,ST
J3.22	PC23	GPIO	SPI1_MOSI		87		PIO,I,PU,ST
J3.23	PC25	GPIO	SPI1_NCS0		89		PIO,I,PU,ST
J3.24	PC22	GPIO	SPI1_MISO		86		PIO,I,PU,ST
J3.25	PC24	GPIO	SPI1_SPCK		88		PIO,I,PU,ST
J3.26	PC26	GPIO	SPI1_NCS1	TWD1	90		PIO,I,PU,ST
J3.27	GND						PIO,I,PU,ST
J3.28	PC27	GPIO	SPI1_NCS2	TWCK1	91		PIO,I,PU,ST
J3.29	PC28	GPIO	SPI1_NCS3		92		PIO,I,PU,ST
J3.30	PC30	GPIO	UTXD0 (/dev/ttyS5)		94		PIO,I,PU,ST
J3.31	PC29	GPIO	URXD0 (/dev/ttyS5)		93		PIO,I,PU,ST
J3.32	PC31	GPIO			95		PIO,I,PU,ST
J3.33	PA17	GPIO			17		PIO,I,PU,ST
J3.34	PA16	GPIO			16		PIO,I,PU,ST
J3.35	PA19	GPIO		TXCK2	19		PIO,I,PU,ST
J3.36	PA18	GPIO		TWD2	18		PIO,I,PU,ST
J3.37	PA21	GPIO			21		PIO,I,PU,ST
J3.38	PA20	GPIO			20		PIO,I,PU,ST
J3.39	PA23	GPIO			23		PIO,I,PU,ST
J3.40	PA22	GPIO			22		PIO,I,PU,ST
J3.41	PA31	TWCK0	GPIO	UTXD1 (/dev/ttyS6)	31		PIO,I,PU,ST
J3.42	PA30	TWD0	GPIO	URXD1 (/dev/ttyS6)	30		PIO,I,PU,ST
J3.43	PE31	GPIO			159		PIO,I,PD,ST
J3.44	PE29	GPIO			157		PIO,I,PD,ST
J3.45	PC16	SSC_TK0	GPIO		80		PIO,I,PU,ST
J3.46	PC17	SSC_TF0	GPIO		81		PIO,I,PU,ST
J3.47	PC18	SSC_TD0	GPIO		82		PIO,I,PU,ST
J3.48	PC19	SSC_RK0	GPIO		83		PIO,I,PU,ST
J3.49	PC20	SSC_RF0	GPIO		84		PIO,I,PU,ST
J3.50	PC21	SSC_RD0	GPIO		85		PIO,I,PU,ST

JTag signals

Microchip MPU SAMA5D31 datasheet

BOOT_OFF: keeping this line low at startup will disable the boot of the NAND FLASH chip, in order to be able to re-program it with the Microchip tool SAM-BA. If not used can be left disconnected.
VBAT: if you need the internal RTC working you have to connect a backup battery here, also to enable the timed wakeup as explained above. If not used can be left disconnected.

Aria G25 pinout

Pin # AriaG25 pin name
IC Pin Atmel pin name
Primary Line functions assigned by default at reset
Alt Alternative function that can be set changing the device tree binding
ID 2.6.x Kernel 2.6.x ID using sysfs gpio interface
ID 3.11.x Kernel 3.11.x ID using sysfs gpio interface
Note Any notes about the pin
Reset state Line state at CPU reset
- PIO indicates whether the PIO Line resets in I/O mode
- A indicates whether the peripheral A mode
- I/O Indicates whether the signal is input or output state.
- PU/PD Indicates whether Pull-Up, Pull-Down or nothing is enabled.
- ST Indicates if Schmitt Trigger is enabled.

The PIO lines called PAx, PBx and PCx can be configured in up to four different ways. Please refer to the ATSAM9G25 datasheet to have a complete reference.

Be carefull to check whether the line reset state is compatible with your application board because it is changed to the Linux default config during the bootstrap after at least 500 ms.

Pin #	IC Pin	Primary	Alt	ID 2.6x	ID 3.1x	Note	Reset state
N1		3V3				Power In Vcc
N2	PC0	GPIO	SDA1	96	64	I2C bus 1 Data or GPIO	PIO,I,PU,ST
N3	PC1	GPIO	SCL1	97	65	I2C bus 1 Clock or GPIO	PIO,I,PU,ST
N4	PC2	GPIO	TIOA3	98	66	GPIO or TC block PWM0	PIO,I,PU,ST
N5	PC3	GPIO	TIOB3	99	67	GPIO or TC block PWM1	PIO,I,PU,ST
N6	PC4	GPIO		100	68		PIO,I,PU,ST
N7	PC5	GPIO	TIOA4	101	69	GPIO or TC block PWM2	PIO,I,PU,ST
N8	PC6	GPIO	TIOB4	102	70	GPIO or TC block PWM3	PIO,I,PU,ST
N9	PC7	GPIO		103	71		PIO,I,PU,ST
N10	PC8	GPIO	UTXD0	104	72		PIO,I,PU,ST
N11	PC9	GPIO	URXD0	105	73		PIO,I,PU,ST
N12	PC10	GPIO		106	74		PIO,I,PU,ST
N13	PC11	GPIO		107	75		PIO,I,PU,ST
N14	PC12	GPIO	TIOA5	108	76	GPIO or TC block PWM4	PIO,I,PU,ST
N15	PC13	GPIO	TIOB5	109	77	GPIO or TC block PWM5	PIO,I,PU,ST
N16	PC14	GPIO		110	78		PIO,I,PU,ST
N17	PC15	GPIO		111	79		PIO,I,PU,ST
N18	PC16	GPIO	UTXD1	112	80		PIO,I,PU,ST
N19	PC17	GPIO	URXD1	113	81		PIO,I,PU,ST
N20	PC18	GPIO	PWM0	114	82	GPIO or Pulse Width Modulation Out 0	PIO,I,PU,ST
N21	PC19	GPIO	PWM1	115	83	GPIO or Pulse Width Modulation Out 1	PIO,I,PU,ST
N22	PC20	GPIO	PWM2	116	84	GPIO or Pulse Width Modulation Out 2	PIO,I,PU,ST
N23	PC21	GPIO	PWM3	117	85	GPIO or Pulse Width Modulation Out 3	PIO,I,PU,ST
N24		GND				Power In GND

Pin #	IC Pin	Primary	Alt	ID 2.6x	ID 3.1x	Note	Reset state
E1		GND				Power In GND
E2	PC22	TXD3	GPIO	118	86	Serial line /dev/ttyS4 TXD or GPIO	PIO,I,PU,ST
E3	PC23	RXD3	GPIO	119	87	Serial line /dev/ttyS4 RXD or GPIO	PIO,I,PU,ST
E4	PC24	RTS3	GPIO	120	88	Serial line /dev/ttyS4 RTS or GPIO	PIO,I,PU,ST
E5	PC25	CTS3	GPIO	121	89	Serial line /dev/ttyS4 CTS or GPIO	PIO,I,PU,ST
E6	PC26	GPIO		122	90		PIO,I,PU,ST
E7	PC27	RTS1	GPIO	123	91	Serial line /dev/ttyS2 RTS or GPIO	PIO,I,PU,ST
E8	PC28	CTS1	GPIO	124	92	Serial line /dev/ttyS2 CTS or GPIO	PIO,I,PU,ST
E9	PC29	GPIO		125	93		PIO,I,PU,ST
E10	PC30	GPIO		126	94		PIO,I,PU,ST
E11	PC31	GPIO		127	95		PIO,I,PU,ST
E12	USBCP	D+				USB 2.0 Host full-speed port C
E13	USBCN	D-				USB 2.0 Host full-speed port C
E14		GND				Power In GND
E15	USBBN	D-				USB 2.0 Host hi-speed port B
E16	USBBP	D+				USB 2.0 Host hi-speed port B
E17		GND				Power In GND
E18	USBAN	D-				USB 2.0 Host/Device hi-speed port A
E19	USBAP	D+				USB 2.0 Host/Device hi-speed port A
E20	VBAT					RTC battery backup +3 volt DC input
E21	NRST					Reset input signal (active low)
E22	SHDN					Shutdown output signal (active low)
E23	WKUP					Wake-up input signal (active low)
E24		3V3				Power In Vcc

Pin #	IC Pin	Primary	Peripheral A	ID 2.6x	ID 3.1x	Note	Reset state
S1		3V3				Power In Vcc
S2	PA21	1W	GPIO	53	21	Bit banging 1-wire bus or GPIO	PIO,I,PU,ST
S3	PA20	DA3		52	20	microSD Card memory	PIO,I,PU,ST
S4	PA19	DA2		51	19	microSD Card memory	PIO,I,PU,ST
S5	PA18	DA1		50	18	microSD Card memory	PIO,I,PU,ST
S6	PA17	CK		49	17	microSD Card memory	PIO,I,PU,ST
S7	PA16	CDA		48	16	microSD Card memory	PIO,I,PU,ST
S8	PA15	DA0		47	15	microSD Card memory	PIO,I,PU,ST
S9	PA14	NPCS0	GPIO	46	14	SPI bus 0 chip select 0 or GPIO	PIO,I,PU,ST
S10	PA13	SPCK	GPIO	45	13	SPI bus 0 clock or GPIO	PIO,I,PU,ST
S11	PA12	MOSI	GPIO	44	12	SPI bus 0 Master Output or GPIO	PIO,I,PU,ST
S12	PA11	MISO	GPIO	43	11	SPI bus 0 Master Input or GPIO	PIO,I,PU,ST
S13	PA10	DTXD		42	10	Debug serial port	PIO,I,PU,ST
S14	PA9	DRXD		41	9	Debug serial port	PIO,I,PU,ST
S15	PA8	RXD2	GPIO	40	8	Serial line /dev/ttyS3 RXD or GPIO	PIO,I,PU,ST
S16	PA7	TXD2	GPIO	39	7	Serial line /dev/ttyS3 TXD or GPIO	PIO,I,PU,ST
S17	PA6	RXD1	GPIO	38	6	Serial line /dev/ttyS2 RXD or GPIO	PIO,I,PU,ST
S18	PA5	TXD1	GPIO	37	5	Serial line /dev/ttyS2 TXD or GPIO	PIO,I,PU,ST
S19	PA4	GPIO		36	4		PIO,I,PU,ST
S20	PA3	CTS0	GPIO	35	3	Serial line /dev/ttyS1 CTS or GPIO	PIO,I,PU,ST
S21	PA2	RTS0	GPIO	34	2	Serial line /dev/ttyS1 RTS or GPIO	PIO,I,PU,ST
S22	PA1	RXD0	GPIO	33	1	Serial line /dev/ttyS1 RXD or GPIO	PIO,I,PU,ST
S23	PA0	TXD0	GPIO	32	0	Serial line /dev/ttyS1 TXD or GPIO	PIO,I,PU,ST
S24		GND				Power In GND

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note	Reset state
W1		GND				Power In GND
W2		ETHRXP				Eth RX+
W3		ETHRXN				Eth RX-
W4		ETHTXP				Eth TX+
W5		ETHTXN				Eth TX-
W6		ETH3V3				Eth 3V3
W7		ETHLED1				Eth Yellow led (traffic)
W8		ETHLED2				Eth Green led (link)
W9	PA22	GPIO		54	22		PIO,I,PU,ST
W10	PA23	GPIO		55	23		PIO,I,PU,ST
W11	PA24	GPIO	TK	56	24		PIO,I,PU,ST
W12	PA25	GPIO	TF	57	25		PIO,I,PU,ST
W13	PA26	GPIO	TD	58	26		PIO,I,PU,ST
W14	PA27	GPIO	RD	59	27		PIO,I,PU,ST
W15	PA28	GPIO	RK	60	28		PIO,I,PU,ST
W16	PA29	GPIO	RF	61	29		PIO,I,PU,ST
W17	PA30	SDA0	GPIO	62	30	I2C bus 0 Data or GPIO	PIO,I,PU,ST
W18	PA31	SCL0	GPIO	63	31	I2C bus 0 Clock or GPIO	PIO,I,PU,ST
W19	ADVREF					A/D converter voltage reference In (max 3.3 volt)
W20	PB11	AD0	GPIO	75	43	A/D converter Input 0 or GPIO	PIO,I,PU,ST
W21	PB12	AD1	GPIO	76	44	A/D converter Input 1 or GPIO	PIO,I,PU,ST
W22	PB13	AD2	GPIO	77	45	A/D converter Input 2 or GPIO	PIO,I,PU,ST
W23	PB14	AD3	GPIO	78	46	A/D converter Input 3 or GPIO	PIO,I,PU,ST
W24		3V3				Power In Vcc

Arietta pinout

This is the default pinout of Arietta G25 when you use the latest default image available in the image repository.

It is possible to change it by using the Device tree compiler and dynamic Arietta G25 pinout page

Debug port pinout

This port is designed to be used with the Debug Port Interface to have access to the debug messages sent by the Atmel MPU at startup (RomBOOT), during AT91Bootstrap second level boot loader and the Linux Kernel bootstrap.

From this port is is possible to Login directly to the Linux console using a simple serial terminal emulator on your PC.

Pin #	Signal	Dir	Description
DP.1	3V3 power out	OUT	Output from the internal regulator from 5 to 3.3 volt
DP.2	EN5V input	INP	If low turn off internal regulator from 5 to 3.3 volt
DP.3	DTXD	OUT	Debug port serial output at 115200,N,8,1 3V3 level
DP.4	DRXD	INP	Debug port serial input
DP.5	WKUP	INP	Atmel MPU wakeup signal
DP.6	GND		Signal ground

WiFi module placement pinout

This port is designed to place this WiFi module.
To know hot to configure it:

Pin #	Signal	Dir	Description
7	WPS	OUT	WSP function. Low level activated. Wired to PC16
6	LED	N.C.	WiFi module activity led. Not used
5	GND		Signal ground GND
4	USB B D+		USB Host B D+
3	USB B D-		USB Host B D-
2	VCC 3.3V DC	OUT	Output from the internal regulator from 5 to 3.3 volt
1	WiFi TXEN	OUT	RF on/off control. Low level activated to off. Wired to PC30

Schematic

To know more about how are routed each signal inside the Arietta board please take a look to the Arietta schematic.

RoadRunner pinout

TERRA board Daisy connectors pin-out

D10 - ttyS4 and I2C bus 0

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D10.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D10.2	PC22	TXD3	GPIO	118	86	E2	Serial line TXD /dev/ttyS4
D10.3	PC23	RXD3	GPIO	119	87	E3	Serial line RXD /dev/ttyS4
D10.4	PC24	RTS3	GPIO	120	88	E4	Serial line RTS /dev/ttyS4
D10.5	PC25	CTS3	GPIO	121	89	E5	Serial line CTS /dev/ttyS4
D10.6	PC26	GPIO		122	90	E6
D10.7	PA30	SDA0	GPIO	30	62	W17	I2C Bus 0 /dev/i2c-0 data
D10.8	PA31	SCL0	GPIO	31	63	W18	I2C Bus 0 /dev/i2c-0 clock
D10.9		5V0					Power supply 5V
D10.10		GND				N24, E1, S24, W1	Power supply GND

D11 - 8 GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D11.1		3V3				N1, E24, S1, W24	Power supply 3V3
D11.2	PC16	GPIO	UTXD1	112	80	N18	GPIO or TXD /dev/ttyS6
D11.3	PC17	GPIO	URXD1	113	81	N19	GPIO or RXD /dev/ttyS6
D11.4	PC18	GPIO	PWM0	114	82	N20	GPIO or PWM output (hw)
D11.5	PC19	GPIO	PWM1	115	83	N21	GPIO or PWM output (hw)
D11.6	PC20	GPIO	PWM2	116	84	N22	GPIO or PWM output (hw)
D11.7	PC21	GPIO	PWM3	117	85	N23	GPIO or PWM output (hw)
D11.8	PC2	GPIO	TIOA3	98	66	N4	GPIO or PWM output (tc)
D11.9	PC3	GPIO	TIOB3	99	67	N5	GPIO or PWM output (tc)
D11.10		GND				N24, E1, S24, W1	Power supply GND

D12 - 8 GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D12.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D12.2	PC8	GPIO	UTXD0	104	72	N10	GPIO or TXD /dev/ttyS5
D12.3	PC9	GPIO	URXD0	105	73	N11	GPIO or RXD /dev/ttyS5
D12.4	PC10	GPIO	PWM0	106	74	N12	GPIO or PWM output (hw)
D12.5	PC11	GPIO	PWM1	107	75	N13	GPIO or PWM output (hw)
D12.6	PC12	GPIO	TIOA5	108	76	N14	GPIO or PWM output (tc)
D12.7	PC13	GPIO	TIOB5	109	77	N15	GPIO or PWM output (tc)
D12.8	PC14	GPIO		110	78	N16
D12.9	PC15	GPIO		111	89	N17
D12.10		GND				N24, E1, S24, W1	Power supply GND

D13 - tty2 and GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D13.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D13.2	PA5	TXD1	GPIO	37	5	S18	Serial line TXD /dev/ttyS2
D13.3	PA6	RXD1	GPIO	38	6	S17	Serial line RXD /dev/ttyS2
D13.4	PC27	RTS1	GPIO	123	91	E7	Serial line RTS /dev/ttyS2
D13.5	PC28	CTS1	GPIO	124	92	E8	Serial line CTS /dev/ttyS2
D13.6	PC29	GPIO		125	93	E9
D13.7	PC0	GPIO	SDA1	96	64	N2	GPIO or I2C bus 1 /dev/i2c-1 data
D13.8	PC1	GPIO	SCL1	97	65	N3	GPIO or I2C bus 1 /dev/i2c-1 clock
D13.9		5V0					Power supply
D13.10		GND				N24, E1, S24, W1	Power supply GND

D14 - ADC or GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D14.1		3.3V				N1, E24, S1, W24	Power supply 3.3 Volt
D14.2	AVDD	3.24V					Clean 3.24V out for A/D circuitry
D14.3	ADVREF					W19
D14.4		GND				N1, E24, S1, W24	Power supply 3.3 Volt
D14.5	PB11	AD0	GPIO	75	43	W23
D14.6	PB12	AD1	GPIO	76	44	W22
D14.7	PB13	AD2	GPIO	77	45	W21
D14.8	PB14	AD3	GPIO	78	46	W20
D14.9		5V0					Power supply 5 Volt
D14.10		GND				N24, E1, S24, W1	Power supply GND

D15 - SPI bus 0 or GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D15.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D15.2	PA12	SPI-0 MOSI	GPIO	44	12	S11
D15.3	PA11	SPI-0 MISO	GPIO	43	13	S12
D15.4	PA13	SPI-0 SPCK	GPIO	45	14	S10
D15.5	PA14	SPI-0 NPCS0	GPIO	46	15	S9
D15.6	PA7	SPI-0 NPCS1	GPIO	39	7	S16
D15.7	PA1	RXD0	SPI-0 NPCS2	33	1	S22
D15.8
D15.9		5V0					Power supply 5 Volt
D15.10		GND				N24, E1, S24, W1	Power supply GND

D16 - SSC (I2S) and I2C bus 0 or GPIO

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D16.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D16.2	PA29	GPIO	RF	61	29	W16
D16.3	PA27	GPIO	RD	59	27	W14
D16.4	PA24	GPIO	TK	56	24	W11
D16.5	PA25	GPIO	TF	57	25	W12
D16.6	PA26	GPIO	TD	58	26	W13
D16.7	PA30	SDA0	GPIO	63	31	E9	I2C bus 0 /dev/i2c-0 data
D16.8	PA31	SCL0	GPIO	62	30	E11	I2C bus 0 /dev/i2c-0 data
D16.9	PA28	GPIO	RK	60	28	W15
D16.10		GND				N24, E1, S24, W1	Power supply GND

D17 - tty1 and I2C bus 0 or GPIO (optional)

Note: This connector is not available on the TERRA-M because is covered by the GSM module.

On the TERRA board (basic model without the GPRS module) it is not mounted by default. If you need it please ask for a special version.

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Aria pin	Note
D17.1		3V3				N1, E24, S1, W24	Power supply 3.3 Volt
D17.2	PA0	TXD0	GPIO	32	0	S23	Serial line TXD /dev/ttyS1
D17.3	PA1	RXD0	GPIO	33	1	S22	Serial line RXD /dev/ttyS1
D17.4	PA2	RTS0	GPIO	34	2	S21	Serial line RTS /dev/ttyS1
D17.5	PA3	CTS0	GPIO	35	3	S20	Serial line CTS /dev/ttyS1
D17.6	PA4	GPIO		36	4	S19
D17.7	PC0	GPIO	SDA1	96	64	N2	GPIO or I2C bus 1 /dev/i2c-1 data
D17.8	PC1	GPIO	SCL1	97	65	N3	GPIO or I2C bus 1 /dev/i2c-1 clock
D17.9		5V0					Power supply 5 Volt
D17.10		GND				N24, E1, S24, W1	Power supply GND

FOXG20 pinout

J6 pinstrip pads

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
J6.1		3.3V				Power line 3.3 Volt
J6.2		3.3V				Power line 3.3 Volt
J6.3	PB28	RTS1	GPIO	92	60	/dev/ttyS2 RTS
J6.4	PB7	RXD1	GPIO	71	39	/dev/ttyS2 RXD
J6.5	PB6	TXD1	GPIO	70	38	/dev/ttyS2 TXD
J6.6	PB29	CTS1	GPIO	93	61	/dev/ttyS2 CTS
J6.7	PB26	RTS0	GPIO	90	58	/dev/ttyS1 RTS
J6.8	PB5	RXD0	GPIO	69	37	/dev/ttyS1 RXD
J6.9	PB4	TXD0	GPIO	68	36	/dev/ttyS1 TXD
J6.10	PB27	CTS0	GPIO	91	59	/dev/ttyS1 CTS
J6.11
J6.12		5V				Power line 5 Volt
J6.13	PB11	RXD3	GPIO	75	43	/dev/ttyS4 RXD
J6.14	PB10	TXD3	GPIO	74	42	/dev/ttyS4 TXD
J6.15	PB13	GPIO		77	45
J6.16	PB12	GPIO		76	44
J6.17	PB21	GPIO		85	53
J6.18	PB20	GPIO		84	52
J6.19	PB31	GPIO		95	63
J6.20	PB30	GPIO		94	62
J6.21	PA31	GPIO		63	31
J6.22	PA30	GPIO		62	30
J6.23
J6.24	PA6	GPIO		38	6
J6.25	PA7	GPIO		39	7
J6.26	PA9	GPIO		41	9
J6.27	PC3	AD3	NPCS3	99	67	Analog input 3 or SPI bus chip select 3
J6.28	PC2	AD2	GPIO	98	66	Analog input 2
J6.29	PC1	AD1	GPIO	97	65	Analog input 1
J6.30	PC0	AD0	GPIO	96	64	Analog input 0
J6.31	PA24	SCL	GPIO	56	24	I2C Clock
J6.32	PA23	SCD	GPIO	55	23	I2C Data
J6.33	AVDD					Clean 3.3V out for A/D circuitry
J6.34	VREF					A/D voltage reference input
J6.35	AGND					Analog ground
J6.36	PA10	GPIO		42	10
J6.37	PA22	GPIO		54	22
J6.38	PA11	GPIO		43	11
J6.39		GND				Power line GND
J6.40		GND				Power line GND

J7 pinstrip pads

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
J7.1		GND				Power line GND
J7.2		GND				Power line GND
J7.3	PB18	GPIO		82	50
J7.4	PB19	GPIO		83	51
J7.5	PB16	GPIO		80	48
J7.6	PB17	GPIO		81	49
J7.7	PB2	CK	GPIO	66	34	SPI bus clock
J7.8	PB3	NPCS0	GPIO	67	35	SPI CS0
J7.9	PB0	MISO	GPIO	68	36	SPI MISO
J7.10	PB1	MOSI	GPIO	69	37	SPI MOSI
J7.11	PC14	GPIO		110	78	Signal level at 1.8V
J7.12	PC15	GPIO		111	79	Signal level at 1.8V
J7.13	PC12	GPIO		108	76	Signal level at 1.8V
J7.14	PC13	GPIO		109	77	Signal level at 1.8V
J7.15	PC9	GPIO		105	73	Signal level at 1.8V
J7.16	PC10	CTS3	GPIO	106	74	/dev/ttyS4 CTS at 1.8V.
J7.17	PC7	GPIO		103	71	Wired on PC7 red led. Signal level at 1.8V
J7.18	PC8	RTS3	GPIO	104	72	/dev/ttyS4 RTS. Signal level at 1.8V
J7.19	PC5	NPCS1	GPIO	101	69	SPI bus CS1
J7.20	PC6	GPIO		102	70	Reserved. Used to read if the client USB port is wired to a PC
J7.21	PB9	RXD2	GPIO	73	41	/dev/ttyS3 RXD
J7.22	PB8	TXD2	GPIO	72	40	/dev/ttyS3 TXD
J7.23		BATT				RTC Battery input, Use this terminal to wire an external 3.3 volt RTC backup battery
J7.24		PGD				Wired to power good line on Netus PS1
J7.25		POK				Wired to power ok line on Netus PS1
J7.26		SHDNPS#				PS1 shutdown. Active low
J7.27	NRST					Active low CPU reset input line
J7.28	SHDN#					Wired to the SHDN Netus G20 line
J7.29		5V				5 volt power line
J7.30		WAKEUP				Wired to the WAKEUP Netus G20 line
J7.31	PB23	GPIO		87	55
J7.32	PB22	GPIO		86	54
J7.33	PB25	GPIO		89	57
J7.34	PB24	GPIO		88	56
J7.35	PA28	GPIO		60	28
J7.36	PA27	GPIO		59	27
J7.37	PA26	GPIO		58	26
J7.38	PA25	GPIO		57	25
J7.39		3.3V				Power line 3.3 Volt
J7.40		3.3V				Power line 3.3 Volt

Netus G20 pinout

All the signals available on the Netus G20 connectors are linked directly to the CPU except BATT IN (J1.17 - J3.18). Refer to the AT91SAM9G20 datasheet to know the CPU signals function

J1 and J3 signals

J1 (top side) and J3 (bottom side) connectors share the same signals.

Top	Bottom	CPU Signal	Function	Type	Comments
J1.1	J3.1	3V3		Power
J1.2	J3.2	3V3		Power
J1.3	J3.3	JTAG TDO	Test data out	Output
J1.4	J3.4	HDMA
J1.5	J3.5	JTAG TDI	Test data in	Input
J1.6	J3.6	HDPA
J1.7	J3.7	JTAG NTRST	Test reset signal	Input
J1.8	J3.8	GND	Ground	Ground
J1.9	J3.9	JTAG RTCK	Return test clock	Output
J1.10	J3.10	HDPB
J1.11	J3.11	JTAG SEL	JTAG Selection	Input
J1.12	J3.12	HDMB
J1.13	J3.13	JTAG TCK	Test clock	Input
J1.14	J3.14	GND	Ground	Ground
J1.15	J3.15	JTAG TMS	Test mode select	Input
J1.16	J3.16	DDP
J1.17	J3.17	BATT IN		Battery backup 3V input
J1.18	J3.18	DDM
J1.19	J3.19	1V0		Power
Top	Bottom	CPU Signal	Function	Type	Comments
J1.20	J3.20	1V0		Power
J1.21	J3.21	SHDN#	Shutdown control	Output
J1.22	J3.22	WAKE UP	Wake-up input	Input
J1.23	J3.23	NRST
J1.24	J3.24	GND	Ground	Ground
J1.25	J3.25	PB19	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.26	J3.26	PB18	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.27	J3.27	PB17	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.28	J3.28	PB16	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.29	J3.29	PB15	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.30	J3.30	PB14	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.31	J3.31	PB9	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.32	J3.32	PB8	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.33	J3.33	PB7	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.34	J3.34	PB6	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.35	J3.35	PB5	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.36	J3.36	PB4	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.37	J3.37	PB3	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.38	J3.38	PB2	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.39	J3.39	PB1	Parallel IO Controller B	I/O	Pulled-up input at reset
Top	Bottom	CPU Signal	Function	Type	Comments
J1.40	J3.40	PB0	Parallel IO Controller B	I/O	Pulled-up input at reset
J1.41	J3.41	1V8		Power
J1.42	J3.42	1V8		Power
J1.43	J3.43	PC15	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.44	J3.44	PC14	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.45	J3.45	PC13	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.46	J3.46	PC12	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.47	J3.47	PC11	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.48	J3.48	PC10	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.49	J3.49	PC9	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.50	J3.50	PC8	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.51	J3.51	PC7	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.52	J3.52	PC6	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.53	J3.53	PC5	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.54	J3.54	PC4	Parallel IO Controller C	I/O	Pulled-up input at reset
J1.55	J3.55	FREE1	Available
J1.56	J3.56	FREE2	Available
J1.57	J3.57	FREE3	Available
J1.58	J3.58	FREE4	Available
J1.59	J3.59	GND	Ground	Ground
J1.60	J3.60	GND	Ground	Ground

J2 and J4 signals

J2 (top side) and J4 (bottom side) connectors share the same signals.

Top	Bottom	Signal name	Function	Type	Comments
J2.1	J4.1	3V3
J2.2	J4.2	3V3
J2.3	J4.3	PA31	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.4	J4.4	PA30	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.5	J4.5	PA29	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.6	J4.6	PA28	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.7	J4.7	PA27	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.8	J4.8	PA26	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.9	J4.9	PA25	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.10	J4.10	PA24	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.11	J4.11	PA23	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.12	J4.12	PA22	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.13	J4.13	PA21	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.14	J4.14	PA20	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.15	J4.15	PA19	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.16	J4.16	PA18	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.17	J4.17	PA17	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.18	J4.18	PA16	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.19	J4.19	PA15	Parallel IO Controller A	I/O	Pulled-up input at reset
Top	Bottom	Signal name	Function	Type	Comments
J2.20	J4.20	PA14	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.21	J4.21	PA13	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.22	J4.22	PA12	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.23	J4.23	PA11	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.24	J4.24	PA10	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.25	J4.25	PA9	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.26	J4.26	PA8	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.27	J4.27	PA7	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.28	J4.28	PA6	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.29	J4.29	PA5	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.30	J4.30	PA4	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.31	J4.31	PA3	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.32	J4.32	PA2	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.33	J4.33	PA1	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.34	J4.34	PA0	Parallel IO Controller A	I/O	Pulled-up input at reset
J2.35	J4.35	PB31	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.36	J4.36	PB30	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.37	J4.37	PB29	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.38	J4.38	PB28	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.39	J4.39	PB27	Parallel IO Controller B	I/O	Pulled-up input at reset
Top	Bottom	Signal name	Function	Type	Comments
J2.40	J4.40	PB26	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.41	J4.41	PB25	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.42	J4.42	PB24	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.43	J4.43	PB23	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.44	J4.44	PB22	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.45	J4.45	PB21	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.46	J4.46	PB20	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.47	J4.47	PB13	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.48	J4.48	PB12	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.49	J4.49	PB11	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.50	J4.50	PB10	Parallel IO Controller B	I/O	Pulled-up input at reset
J2.51	J4.51	PC3	Parallel IO Controller C	I/O	Pulled-up input at reset
J2.52	J4.52	PC2	Parallel IO Controller C	I/O	Pulled-up input at reset
J2.53	J4.53	PC1	Parallel IO Controller C	I/O	Pulled-up input at reset
J2.54	J4.54	PC0	Parallel IO Controller C	I/O	Pulled-up input at reset
J2.55	J4.55	AGND
J2.56	J4.56	AGND
J2.57	J4.57	AVDD
J2.58	J4.58	VREF
J2.59	J4.59	GND
J2.60	J4.60	GND

YARM pinout

YARM-DEV user application pinout

This is the general purpose pins available for the user applications

YARM-DEV full pinout

This is the full pinout tha include also the special function pins.

The pins in green come directly from the AVR ATA8510 transceiver chip
The pins in blue come directly from the SAM L21 main MPU chip

For a full reference abut the pin functionality please read the Atmel datasheets:

Please note that to program the Atmel ATA8510 it is required to sign a NDA with Microchip/Atmel. To use this chip in normal radio application we provide a royalties free closed source binary firmware.

DAISY-1 pinout

D1 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D1.1		3.3V				Power line 3.3 Volt
D1.2	PB6	TXD1	GPIO	70	38	Serial line /dev/ttyS2 TXD
D1.3	PB7	RXD1	GPIO	71	39	Serial line /dev/ttyS2 RXD
D1.4	PB28	RTS1	GPIO	92	60	Serial line /dev/ttyS2 RTS
D1.5	PB29	CTS1	GPIO	93	61	Serial line /dev/ttyS2 CTS
D1.6
D1.7	PA23	SCD	GPIO	54	22	I2C Bus Data
D1.8	PA24	SCL	GPIO	55	23	I2C Bus Clock
D1.9		5V				Power line 5 Volt
D1.10		GND				Power line GND

D2 connector

Pin #	IC Pin	Default	ID 2.6x	ID 3.1x	Note
D2.1		3.3V			Power line 3.3 Volt
D2.2	PA31	GPIO	63	31	General purpose IO
D2.3	PA30	GPIO	62	30	General purpose IO
D2.4	PA29	GPIO	61	29	General purpose IO
D2.5	PA28	GPIO	60	28	General purpose IO
D2.6	PA27	GPIO	59	27	General purpose IO
D2.7	PA26	GPIO	58	26	General purpose IO
D2.8	PA25	GPIO	57	25	General purpose IO
D2.9	PB30	GPIO	94	62	General purpose IO
D2.10		GND			Power line GND

D3 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D3.1		3.3V				Power line 3.3 Volt
D3.2	PB4	TXD0	GPIO	68	36	Serial line /dev/ttyS1 TXD
D3.3	PB5	RXD0	GPIO	69	37	Serial line /dev/ttyS1 RXD
D3.4	PB26	RTS0	GPIO	90	58	Serial line /dev/ttyS1 RTS
D3.5	PB27	CTS0	GPIO	91	59	Serial line /dev/ttyS1 CTS
D3.6	PB22	GPIO		86	54	General purpose IO
D3.7	PB24	GPIO		88	56	General purpose IO
D3.8	PB25	GPIO		89	57	General purpose IO
D3.9	PB23	GPIO		87	55	General purpose IO
D2.10		GND				Power line GND

D4 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D4.1		3.3V				Power line 3.3 Volt
D4.2		AVDD				Clean 3.3V out for A/D circuitry
D4.3		VREF				A/D voltage reference input
D4.4		AGND				Analog ground
D4.5	PC0	AD0	GPIO	96	64	Analog input 0
D4.6	PC1	AD1	GPIO	97	65	Analog input 1
D4.7	PC2	AD2	GPIO	98	66	Analog input 2
D4.8	PC3	AD3	NPCS3	99	67	Analog input 3 or SPI bus chip select 3
D4.9		5V				Power line 5 Volt
D4.10		GND				Power line GND

D5 connector

Pin #	IC Pin	Default	ID 2.6x	ID 3.1x	Note
D5.1		3.3V			Power line 3.3 Volt
D5.2	PB12	GPIO	76	44	General purpose IO
D5.3	PB13	GPIO	77	45	General purpose IO
D5.4	PB16	GPIO	80	48	General purpose IO
D5.5	PB17	GPIO	81	49	General purpose IO
D5.6	PB18	GPIO	82	50	General purpose IO
D5.7	PB19	GPIO	83	51	General purpose IO
D5.8	PB20	GPIO	84	52	General purpose IO
D5.9	PB21	GPIO	85	53	General purpose IO
D5.10		GND			Power line GND

D6 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D6.1		3.3V				Power line 3.3 Volt
D6.2	PB10	TXD3	GPIO	74	42	Serial line /dev/ttyS4 TXD
D6.3	PB11	RXD3	GPIO	75	43	Serial line /dev/ttyS4 RXD
D6.4		RTS3	GPIO			Serial line /dev/ttyS4 RTS
D6.5		CTS3	GPIO			Serial line /dev/ttyS4 CTS
D6.6	PB31	GPIO		95	63	General purpose IO
D6.7	PA23	SCD	GPIO	55	23	I2C Bus Data
D6.8	PA24	SCL	GPIO	56	24	I2C Bus Clock
D6.9		5V				Power line 5 Volt
D6.10		GND				Power line GND

D7 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D7.1		3.3V				Power line 3.3 Volt
D7.2	PB1	MOSI	GPIO	69	37	SPI bus master output/slave input
D7.3	PB0	MISO	GPIO	68	36	SPI bus master input/slave output
D7.4	PB2	CK	GPIO	66	34	SPI bus clock
D7.5	PB3	NPCS0	GPIO	67	35	SPI bus chip select 0
D7.6		NPCS1	GPIO			SPI bus chip select 1
D7.7		NPCS2	GPIO			SPI bus chip select 2
D7.8		NPCS3	GPIO			SPI bus chip select 3
D7.9		5V				Power line 5 Volt
D7.10		GND				Power line GND

D8 connector

Pin #	IC Pin	Default	Alt	ID 2.6x	ID 3.1x	Note
D8.1		3.3V				Power line 3.3 Volt
D8.2	PB8	TXD2	GPIO	74	42	Serial line /dev/ttyS3 TXD
D8.3	PB9	RXD2	GPIO	73	41	Serial line /dev/ttyS3 RXD
D8.4	N.C.
D8.5	N.C.
D8.6	N.C.
D6.7	PA23	SCD	GPIO	55	23	I2C Bus Data
D6.8	PA24	SCL	GPIO	56	24	I2C Bus Clock
D8.9		5V				Power line 5 Volt
D8.10		GND				Power line GND

Kernel IDs

Port	ID
PA0	0
PA1	1
PA2	2
PA3	3
PA4	4
PA5	5
PA6	6
PA7	7
PA8	8
PA9	9
PA10	10
PA11	11
PA12	12
PA13	13
PA14	14
PA15	15
PA16	16
PA17	17
PA18	18
PA19	19
PA20	20
PA21	21
PA22	22
PA23	23
PA24	24
PA25	25
PA26	26
PA27	27
PA28	28
PA29	29
PA30	30
PA31	31

Port	ID
PB0	32
PB1	33
PB2	34
PB3	35
PB4	36
PB5	37
PB6	38
PB7	39
PB8	40
PB9	41
PB10	42
PB11	43
PB12	44
PB13	45
PB14	46
PB15	47
PB16	48
PB17	49
PB18	50
PB19	51
PB20	52
PB21	53
PB22	54
PB23	55
PB24	56
PB25	57
PB26	58
PB27	59
PB28	60
PB29	61
PB30	62
PB31	63

Port	ID
PC0	64
PC1	65
PC2	66
PC3	67
PC4	68
PC5	69
PC6	70
PC7	71
PC8	72
PC9	73
PC10	74
PC11	75
PC12	76
PC13	77
PC14	78
PC15	79
PC16	80
PC17	81
PC18	82
PC19	83
PC20	84
PC21	85
PC22	86
PC23	87
PC24	88
PC25	89
PC26	90
PC27	91
PC28	92
PC29	93
PC30	94
PC31	95

Port	ID
PD0	96
PD1	97
PD2	98
PD3	99
PD4	100
PD5	101
PD6	102
PD7	103
PD8	104
PD9	105
PD10	106
PD11	107
PD12	108
PD13	109
PD14	110
PD15	111
PD16	112
PD17	113
PD18	114
PD19	115
PD20	116
PD21	117
PD22	118
PD23	119
PD24	120
PD25	121
PD26	122
PD27	123
PD28	124
PD29	125
PD30	126
PD31	127

Port	ID
PE0	128
PE1	129
PE2	130
PE3	131
PE4	132
PE5	133
PE6	134
PE7	135
PE8	136
PE9	137
PE10	138
PE11	139
PE12	140
PE13	141
PE14	142
PE15	143
PE16	144
PE17	145
PE18	146
PE19	147
PE20	148
PE21	149
PE22	150
PE23	151
PE24	152
PE25	153
PE26	154
PE27	155
PE28	156
PE29	157
PE30	158
PE31	159